This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2000-283850, filed on Sep. 19, 2000; the entire contents of which are incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a read channel circuit and method for decoding using reduced-complexity error correction. More particularly, the present invention relates to a technology for providing a read channel circuit which has a decoding function applicable to high channel frequencies for decoding a modulated reception signal and is favorably applicable to an optical disk playback equipment such as a DVD, a CD-ROM, or a MD player.
2. Description of the Related Art
FIG. 1 illustrates a conventional read channel circuit applicable to a playback equipments such as a DVD player.
Such a conventional read channel circuit comprises, as shown in FIG. 1, a comparator 70, a slice level generator 71, a channel clock generator 72, and a flip-flop 73.
The comparator 70 is fed at the positive electrode (+) terminal and the negative electrode (xe2x88x92) terminal with a reception signal (a playback signal) received at the read channel and a slice level signal generated by the slice level generator 71, respectively. The output of the comparator 70 is a low (L) level signal when the input voltage level of the negative electrode is greater than that of the positive electrode, and is a high (H) level signal when the input voltage level of the negative electrode is lower than that of the positive electrode. Therefore, the output of the comparator 70 is a binary signal. The binary signal output of the comparator 70 is then transferred to the slice level generator 71, the channel clock generator 72, and the flip-flop 73.
The slice level generator 71 is responsive to the output signal from the comparator 70 for controlling the voltage of the slice level signal so as to have an average duty ratio of 50%.
The channel clock generator 72 generates a channel clock synchronized in phase with the binary signal from the comparator 70 and transfers the binary signal to a clock terminal of the flip-flop 73. The operation of the channel clock generator 72 shown in FIG. 1 synchronizes the polarity inverted phase of the binary signal with the falling edge phase of the channel clock and sets the duty ratio of the channel clock to 50%. The channel clock generator 72 may be implemented by a PLL (phase locked loop) circuit.
The flip-flop 73 samples the binary signal received at its data input terminal from the comparator 70 at the timing of each rising edge of the channel clock. A sampled signal output from the flip-flop 73 is then transferred as a channel stream signal to a given processor circuit provided at the succeeding stage of the flip-flop 73.
The conventional read channel circuit described above however has the following technical problems.
The technical problems in the conventional read channel circuit will now be described referring to FIG. 2. As shown in FIG. 2, denoted by (1) is a received signal which may represent a pattern of pits provided on a DVD disk. It is also assumed that the signal (1) is encoded by RLL (run-length limited coding) (2,10). In the RLL (2,10), the minimum code inverted length is 3T and the maximum code inverted length is 11T (T represents one channel cycle).
Also, a signal (2) is an ideal received signal from an optical playback path of DVD system as the transmission path. A signal (3) is a slice level signal. A signal (4) is a noise signal superimposed on the transmission path. A signal (5) is a received signal superimposed with the noise signal (4). A signal (6) is an ideal slice level signal. Note that the signal (5) is equivalent to a sum of the two signals (2) and (4).
A signal (7) is a binary signal outputted from the comparator 70 in response to the input of the signal (2). A signal (8) is another binary signal outputted from the comparator 70 in response to the input of the signal (5). A signal (9) is a channel clock synchronized with the signal (7) or (8). A signal (10) is a channel stream signal generated by decoding the signal (2). A signal (11) is another channel stream signal generated by decoding the signal (5).
As apparent from FIG. 2, the channel stream signal (10) from the decoding of the signal (2) is equal in the encoded form to the transmission signal (1) and can thus be decoded without any error. On the other hand, the channel stream signal (11) from the decoding of the signal (5) having noise components added is not equal in the encoded form to the transmission signal (1) as containing errors in the proximity of moments t2, t5, t7 and t8.
In other words, in the conventional read channel circuit, as the noises are superimposed at given levels and given moments on the transmission path, they may result in errors on the channel stream signal. The noises on the transmission path in a DVD player may derive from fault formation of pits, tilting of the optical axis of an optical pickup from the vertical to a disk surface, tracking error, or leak signals of any adjacent track in accordance with deviance in tracking control.
There is commonly proposed a scheme for adding an error correction code to a digital code signal which is carried along the transmission path failing to inhibit the introduction of noises.
Such a scheme may be favored when the number of errors developed on the channel stream signal stays within a range of the capability of error correction of the error correction code. However, if errors exceed the range, they will hardly be eliminated hence making the receive signal incorrect. Alternative technologies are thus desired for minimizing the development of errors on the channel stream prior to the step of error correction with the error correction code.
One of them is disclosed in Japanese Patent Laid-open Application No. PH9-8674 where the development of errors on the channel stream prior to the step of error correction is minimized by means of a maximum likelihood decoder using Viterbi algorithms.
FIG. 3 illustrates a read channel circuit equipped with the maximum likelihood decoder.
The read channel circuit with the maximum likelihood decoder shown in FIG. 3 comprises an analog/digital converter (ADC) 75, an adder 76, a slice level generator 77, a channel clock generator 78, and the maximum likelihood decoder 79.
The ADC 75 samples the received signal at the timing of the channel clock generated by the channel clock generator 78 and quantizes a sampled signal to data of a specific number of bits (for example, 8 bits) which is then transferred as a multi-level signal to the adder 76.
The adder 76 adds the multi-level signal from the ADC 75 with a slice level signal from the slice level generator 77 to have an offset multi-level signal which is transferred to the maximum likelihood decoder 79. Also, sign bit of the offset multi-level signal output of the adder 76 is transmitted to the slice level generator 77 and the channel clock generator 78.
The slice level generator 77 upon receiving the signal output from the adder 76 generates a slice level to have an average duty ratio of 50%. The slice level generator 77 and the adder 76 generates in a combination an auto slice signal which is received by both the channel clock generator 72 and the maximum likelihood decoder 79.
The channel clock generator 78 generates a channel clock synchronized in phase with the sign bit of the offset multi-level signal from the adder 76. The generated channel clock is transferred as a sampling clock signal to the ADC 75 and as an operating clock signal to the slice level generator 77 and the maximum likelihood decoder 79. The channel clock generator 78 may be implemented by a PLL circuit, for example.
The maximum likelihood decoder 79 decodes the received signal using Viterbi algorithms and its resultant decoded signal output is further transferred as a channel stream to a processing circuit provided at the succeeding step. A detailed procedure of the maximum likelihood decoding using Viterbi algorithms is disclosed in, for example, aforementioned Japanese Patent Laid-open Application No. PH9-8674.
However, the conventional read channel circuit when installed in a high-speed playback apparatus may develop the following technical problems.
In case of a DVD playback apparatus, the channel clock frequency reaches 420 MHz at a 16-fold playback speed, while 26.16 MHz at a so-called 1-fold playback speed and 420 MHz at a 16-fold speed. When the conventional read channel circuit is used for such a high-speed playback processing where the sampling of ADC is carried out by the channel clock as shown in FIG. 3, the sampling frequency of 420 MHz is required at the 16-fold speed. Also, with the conventional read channel circuit in the DVD playback apparatus, the number of quantizing bits in ADC is substantially eight.
This will increase the cost of the ADC using the foregoing sampling frequency and the quantizing bits as well as the power consumption and the heat generation. As a system LSI is equipped with the ADC of this type, its installation size will increase and its generation of heat will hardly be negligible. The above described technical problems will thus make it difficult to provide a low-cost DVD-ROM playback apparatus.
According to an aspect of the present invention, there is provided a read channel circuit for decoding a playback signal received from a prescribed transmission path which comprises: a slice level signal generator configured to generate a reference slice level signal and a plurality of slice level signals which are different from the reference slice level signal; a comparator configured to convert the playback signal into a plurality of binary signals synchronized with a channel clock and on the basis of each of the plurality of slice level signals generated; a phase distance measurement unit configured to select two binary signals from the plurality of binary signals and measure a phase distance which represents the number of edges in a prescribed clock between the edges of the two binary signals selected on the basis of the channel clock; an inverted edge detector configured to judge the polarity of an inverted edge of a reference binary signal binarized in accordance with the reference slice level signal among the plurality of binary signals; and an error corrector configured to generate an error correction signal to the playback signal on the basis of the phase distance measured and the polarity of the inverted edge of the reference binary signal detected to perform error correction on the playback signal.
According to another aspect of the present invention, there is provided a method of correcting an error in a playback signal received from a prescribed transmission path which comprises the steps of: generating a reference slice level signal and a plurality of slice level signals which are different from the reference slice level signal; converting the playback signal into a plurality of binary signals synchronized with a channel clock and on the basis of each of the plurality of slice level signals generated; selecting two binary signals from the plurality of binary signals and measuring a phase distance which represents the number of edges in a prescribed clock between the edges of the two binary signals selected on the basis of the channel clock; judging the polarity of an inverted edge of the reference binary signal binarized in accordance with the reference slice level signal among the plurality of binary signals; and generating an error correction signal to the playback signal on the basis of the phase distance measured and the polarity of the inverted edge of the reference binary signal judged to perform error correction.